Field effect transistors generally comprise a source, a drain, a gate, and a channel between the source and drain. The gate is separated from the channel by a thin insulating layer, typically of silicon oxide, called the gate dielectric. The channel is covered by the thin gate dielectric and bordered on two or more sides by an overlying gate structure. A voltage drop generated by the gate across the gate dielectric layer induces a conducting channel between the source and drain, thereby controlling the current flow between the source and the drain. Current integrated circuit designs use complementary metal-oxide-semiconductor (CMOS) technology that use complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.
The integrated circuit industry is continually reducing the size of the devices and increasing the number of circuits that can be produced on a given substrate or chip. Process challenges exist as the dimensions of semiconductor devices decrease, some now falling below 20 nm. As the dimensions of the device decrease, the spacing between the various circuit elements also decreases, leading to increased parasitic capacitance. Parasitic capacitance is the unwanted capacitance that exists between the parts of an electronic component or circuit simply because of their proximity to each other. The increased parasitic capacitance can have detrimental effects on the circuit performance, limiting the frequency response of the device.
The channel in FETs can consist of a fin or nanowire structure. The “fin” is typically a vertically narrow and elongated structure, for example, comprising III-V semiconductor. A nanowire is a structure that can have a diameter on the order of a nanometer.
For present purposes, the term “semiconductor channel” or “channel” are used to generically include both “fin” and “nanowire” that can be used in FinFETs or nanowire FETs.
It would be desirable to decrease or eliminate parasitic capacitance issues transistors employing fin structures or nanowires.